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4
Single-Ended Signals AC Output Parameters Tests
•
•
* Pin Under Test signal can be either one of the signals under the test definition.
Test Definition Notes from the Specification
Table 21
Low Power DDR SDRAM Electrical Characteristics
Parameter/Cond ition
DC Output Low Voltage (IOL = -0.1mA)
PASS Condition
The minimum value for the low level voltage should be less than or equal to the maximum V
value.
Measurement Algorithm
1
2
3
4
5
6
7
8
9
10 Compare the test results against the compliance test limits.
Test References
See Table 8 - Low Power DDR SDRAM Electrical Characteristics, in the JEDEC Standard JESD79E.
60
Data Strobe Signal (DQS as Supporting Signal)
Clock Signal - CK is required to perform pre-test to verify the DUT speed against user's speed
grade selection
Calculate initial time scale value based on the selected DDR1 speed grade options.
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Calculate the number of sampling points according to the time scale value.
Obtain sample or acquire signal data and perform signal conditioning to maximize the screen
resolution (vertical scale adjustment).
Perform signal checking on all the signals in-use in the measurements to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Setup the required scope settings and histogram function settings.
Use the histogram Min value as the test result for V
When multiple trials are performed, the largest value (worst case) among the trials will be used
as the test result for V
OL(AC)
Symbol
Min
VOL
-
OL(AC)
.
DDR1 Compliance Testing Methods of Implementation
Max
Units
0.1 * VDDQ
V
.
Notes
-
OL(AC)
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