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Cycle to Cycle Period Jitter - tJIT(cc) - Test Method of Implementation
This test is applicable to the Rising Edge Measurement as well as Falling Edge Measurement. The
purpose of this test is to measure the difference in the clock period between two consecutive clock
cycles. The tJIT(cc) Rising Edge Measurement measures the clock period from the rising edge of a
clock cycle to the next rising edge. The tJIT(cc) Falling Edge Measurement measures the clock period
from the falling edge to falling edge. The test will show a fail status if the total failed waveforms is
greater than 0.
Signals of Interest
Based on the test definition:
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Signals required to perform the test on the oscilloscope:
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Measurement Algorithm
Example input test signal: Frequency: 1 KHz, Number of cycles acquired: 202.
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DDR1 Compliance Testing Methods of Implementation
Clock Signal
Clock Signal - CK is required to perform pre-test to verify the DUT speed against user's speed
grade selection
Measure the difference between every adjacent pair of periods.
Generate 201 measurement results.
Check the results for the smallest and largest values (worst case values).
Compare the test results against the compliance test limits.
Advanced Debug Mode Clock Tests
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