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8
Clock Timing (CT) Tests
Test Definition Notes from the Specification
Table 51
Electrical Characteristics and AC Timing
AC Characteristics - Parameter
DQS output access time from CK/CK
AC Characteristics - Parameter
DQS output access time from CK/CK
Table 52
AC Timing Variations for DDR 333, DDR 266 & DDR 200 Devices
Parameter
DDR 333B
Min
Max
tDQSCK
-0.7
0.7
PASS Condition
The measured time interval between the data strobe access output and the rising edge of the clock
should be within the specification limit.
Measurement Algorithm
1
2
3
4
5
6
7
8
9
10 After obtaining the Edge number for the respective signal, begin the tDQSCK measurement bit by
11 Continue the measurement until last bit (for example, until a tristate happens, which indicates
12 The DQS-Clock timing measurement compares the rising edge (DQS crossing against clock
13 Within the data burst, measure each bit, for instance the rising and falling edge of the
126
Symbol
Min
tDQSCK
-0.60
Symbol
DDR 400A (2.5-3-3)
Min
tDQSCK
-0.6
DDR 266A
Min
Max
-0.75
0.75
Obtain the parameters and settings from the Configuration page.
Pre-condition the scope setting. Verify the actual DUT speed against the user speed selection at
the Setup page.
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Chip Select (CS) option is only applicable if the user has selected "Yes" for the Verify Selected
Rank Only option in the Configuration page. It uses the CS-DQS for signal separation. Else, by
default, the DQS-DQ is used for signal separation.
Use the InfiniiScan feature with the Setup time and Hold time to find and capture the Read cycle.
If you have selected the CS option, skip the next step and go to step 9.
Search for the DQS preamble towards the left from the point where the Read cycle was previously
captured. The For loops, TEdge and Delta Time are used to search the preamble.
Once the preamble is located, call the "BinaryEdgeNormal" function to obtain the Edge number.
This Edge number will be used to locate the point of interest on the specific signal.
bit in the Read data burst. Begin at the 1st bit of the Read cycle, from the Read preamble.
the end of a data burst for the respective Read cycle).
crossing) OR the falling edge (DQS crossing against clock crossing).
DQS-Clock. Capture the worst case data each time a new value is measured.
DDR 333
DDR 266
Max
Min
Max
+0.60
-0.75
+0.75
DDR 400B (3-3-3)
Max
Min
Max
+0.6
-0.6
+0.6
DDR 266B
DDR 200
Min
Max
Min
-0.75
0.75
-0.8
DDR1 Compliance Testing Methods of Implementation
DDR 200
Units
Min
Max
-0.8
+0.8
ns
DDR 400C (3-4-4)
Units
Min
Max
-0.6
+0.6
ns
DDR 200B
Max
Min
Max
0.8
-0.8
0.8
Notes
Notes
Units
ns
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