Average High Pulse Wid Th - Tch(Avg) - Test Method Of Implementation; Average High Pulse Width - Tch(Avg) - Test Method Of Implementation; Signals Of Interest; Test Definition Notes From The Specification - Keysight U7233A Testing Notes

8 Clock Timing (CT) Tests

Average High Pulse Width - tCH(avg) - Test Method of Implementation

The purpose of this test is to measure the average duty cycle of all the positive pulse widths within a
window of 200 consecutive cycles.

Signals of Interest

Based on the test definition:
•
Signals required to perform the test on the oscilloscope:
•

Test Definition Notes from the Specification.

Table 55 Electrical Characteristics and AC Timing
AC Characteristics Parameter
CK high-level width
AC Characteristics Parameter
CK high-level width

Pass Condition

The tCH measurement value should be within the conformance limits as specified in the JEDEC
Standard JESD79E.

Measurement Algorithm

Example input test signal: Frequency: 1 KHz, Number of cycles acquired: 202.
1
2
3
4

Test References

See Table 11 - Electrical Characteristics and AC Timing, in the JEDEC Standard JESD79E.
130
Clock Signal
Clock Signal - CK is required to perform pre-test to verify the DUT speed against user's speed
grade selection
Symbol
Min
tCH 0.45
Symbol DDR 400A (2.5-3-3)
Min
tCH 0.45
Measure the sliding "window" of 200 cycles.
Measure the width of the high pulses (1-200, 2-201 and 3-202) and determine the average value
for this window.
Check the total 3 results for the smallest and largest values (worst case values).
Compare the test results against the compliance test limits.
DDR 333 DDR 266
Max Min Max
0.55 0.45 0.55
DDR 400B (3-3-3)
Max Min Max
0.55 0.45 0.55
DDR1 Compliance Testing Methods of Implementation
DDR 200 Units
Min Max
0.45 0.55 tCK
DDR 400C (3-4-4) Units
Min Max
0.45 0.55 tCK
Notes
Notes