Test References - Keysight U7233A Testing Notes

7
8
9
10 After obtaining the Edge number for the respective signal, begin the tDSS measurement bit by bit
11 Begin at the 1st bit of the Write cycle, from the Write preamble. Continue the measurement until
12 DQS-Clock timing measurement compares the rising edge (DQS falling against clock crossing).
13 DQ-Clock timing measurement compares the falling edge of the DQS to the clock setup time.
14 Once all bits are validated, assign marker A for the clock signal while marker B for the data signal,
15 Measure delta of marker A and marker B and this will be the test result.
16 Compare the test result against the compliance test limit.

Test References

See Table 11 - Electrical Characteristics and AC Timing, in the JEDEC Standard JESD79E.
DDR1 Compliance Testing Methods of Implementation
If you have selected the CS option, skip the next step and go to step 9.
Search for the DQS preamble towards the left from the point where the Write cycle was previously
captured. The For loops, TEdge and Delta Time are used to search the preamble.
Once the preamble is located, call the "BinaryEdgeNormal" function to obtain the Edge number.
This Edge number will be used to locate the point of interest on the specific signal.
in Write data burst.
the last bit (for example, until a tristate happens, which indicates the end of a data burst for the
respective Write cycle).
The worst case data will be captured each time new value is measured.
for the worst case bit.
Data Strobe Timing (DST) Tests 7
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