Table of Contents
Advertisement
8
Clock Timing (CT) Tests
Average Clock Period - tCK(avg) - Test Method of Implementation
This test is applicable to the Rising Edge Measurement as well as the Falling Edge Measurement.
tCK(avg) is average clock period within 200 consecutive cycle window. The tCK(avg) Rising Edge
Measurement measures the period from the rising edge of a cycle to the next rising edge within the
waveform window. The tCK(avg) Falling Edge Measurements measures from the falling edge to the
falling edge.
Signals of Interest
Based on the test definition:
•
Signals required to perform the test on the oscilloscope:
•
Test Definition Notes from the Specification
Table 53
Electrical Characteristics and AC Timing
AC Characteristics - Parameter
Clock cycle time CL = 2.5
Clock cycle time CL = 2
AC Characteristics - Parameter
Clock cycle time CL = 3
Clock cycle time CL = 2.5
Clock cycle time CL = 2
Table 54
AC Timing Variations for DDR 333, DDR 266 & DDR 200 Devices
DDR 333B
tCK CL = 2.5
6
tCK CL = 2.0
7.5
NOTE 30: The only time that the clock frequency is allowed to change is during self-refresh mode.
PASS Condition
The tCK(avg) measurement value should be within the conformance limits as specified in the JEDEC
Standard JESD79E.
128
Clock Signal
Clock Signal - CK is required to perform pre-test to verify the DUT speed against user's speed
grade selection
Symbol
Min
tCK
6
tCK
7.5
Symbol
DDR 400A (2.5-3-3)
tCK
5
tCK
5
tCK
7.5
DDR 266A
12
7.5
12
12
7.5
12
DDR 333
DDR 266
Max
Min
Max
12
7.5
12
12
7.5
12
DDR 400B (3-3-3)
7.5
5
7.5
12
6
12
12
7.5
12
DDR 266B
DDR 200
7.5
12
10
10
12
10
DDR1 Compliance Testing Methods of Implementation
DDR 200
Units
Min
Max
10
12
ns
10
12
ns
DDR 400C (3-4-4)
Units
5
7.5
ns
6
12
ns
10
12
ns
DDR 200B
12
10
12
12
10
12
Notes
30
30
Notes
30
30
30
Units
ns
ns
Advertisement
Table of Contents
