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11
Advanced Debug Mode Clock Tests
Clock Period Jitter - tJIT(per) - Test Method of Implementation
This test is applicable to the Rising Edge Measurement and Falling Edge Measurement. The purpose
of this test is to measure the difference between a measured clock period and the average clock
period across multiple cycles of the clock. You can specify the rising and/or the falling edge of your
signal for this measurement.
Signals of Interest
Based on the test definition (Read cycle only):
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Signals required to perform the test on the oscilloscope:
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Measurement Algorithm
Example input test signal: Frequency: 1 KHz, Number of cycles acquired: 202.
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Clock Signal
Clock Signal - CK is required to perform pre-test to verify the DUT speed against user's speed
grade selection
This measurement measures the difference between every period inside a 200 cycle window with
the average of the whole window.
Compare periods with the new average.
Check the results for the smallest and largest values (worst case values).
Compare the test results against the compliance test limits.
DDR1 Compliance Testing Methods of Implementation
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