Tds(Base), Dq And Dm Input Setup Time - Test Method Of Implementation; Signals Of Interest; Test Definition Notes From The Specification; Pass Condition - Keysight U7233A Testing Notes

tDS(base), DQ and DM Input Setup Time - Test Method of Implementation

The purpose of this test is to verify that the time interval from the data or data mask (DQ/DM
rising/falling Edge) setup time to the associated DQS crossing edge is within the conformance limits
as specified in the JEDEC Standard JESD79E.

Signals of Interest

Based on the test definition (Write cycle only):
•
Signals required to perform the test on the oscilloscope:
•
•
•
Optional signal required to separate the signals for the different Ranks:
•

Test Definition Notes from the Specification

Table 58 Electrical Characteristics and AC Timing
AC Characteristics Parameter
DQ & DM input setup time
AC Characteristics Parameter
DQ & DM input setup time
NOTE j: A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS
slew rates differ. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta
rise, fall rate. Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to
VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)}-{1/(Slew Rate2)}
NOTE k: The 1/0 slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate.
The input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(A) or
VIH(DC) to VIH(DC), and similarly for rising transitions. A derating factor applies to speed bins DDR
200, DDR 266, and DDR 333.
NOTE 31: If refreshing timing or tDS/tDH is violated, data corruption may occur and the data must
be re-written with valid data before a valid READ can be executed.

PASS Condition

The measured time interval between the data or data mask (DQ/DM) setup time to the respective
DQS crossing point should be within the specification limit.
DDR1 Compliance Testing Methods of Implementation
Data Signal (DQ as Pin Under Test Signal)
Data Signal (DQ as Pin Under Test Signal)
Data Strobe Signal (DQS as Supporting Signal)
• Use differential connection (DQS+ and DQS-)
Clock Signal (CK as Reference Signal)
Chip Select Signal (CS as additional signal, which requires additional channel)
Symbol
Min
tDS 0.45
Symbol DDR 400A (2.5-3-3)
Min
tDS 0.4
DDR 333 DDR 266
Max Min Max
0.5
DDR 400B (3-3-3)
Max Min Max
0.4
Data Mask Timing (DMT) Tests
DDR 200 Units
Min Max
0.6 ns
DDR 400C (3-4-4) Units
Min Max
0.4 ns
9
Notes
31, j, k
Notes
31
137