Trpst, Read Postamble - Test Method Of Implementation; Signals Of Interest; Chip Select Signal (Cs As Additional Signal, Which Requires An Additional Channel); Test Definition Notes From The Specification - Keysight U7233A Testing Notes

7 Data Strobe Timing (DST) Tests

tRPST, Read Postamble - Test Method of Implementation

The purpose of this test is to verify that the time when the DQS is no longer driving (from high/low
state to high-impedance) to the last DQS signal crossing (last bit of the data burst) for the Read
cycle is within the conformance limit as specified in the JEDEC Standard JESD79E.

Signals of Interest

Based on the test definition (Read cycle only):
•
Signals required to perform the test on the oscilloscope:
•
•
•
Optional signal required to separate the signals for the different Ranks:

Chip Select Signal (CS as additional signal, which requires an additional channel)

Test Definition Notes from the Specification

Table 47 Electrical Characteristics and AC Timing
AC Characteristics Parameter
Read postamble
AC Characteristics Parameter
Read postamble
NOTE 33: tRPST end; point adn tRPRE begin point are not referenced to a specific voltage level but
specify when the device output is no longer driving (tRPST), or begins driving (tRPRE).

PASS Condition

The measured time interval between the last DQS signal crossing point to the point where the DQS
starts to transit from high/low level to high impedance for the Read cycle should be within the
specification limit.

Measurement Algorithm

1
2
3
4
114
Data Strobe Signal (DQS as Pin Under Test Signal)
Data Strobe Signal (DQS as Pin Under Test Signal)
Data Signal (DQ as Supporting Signal)
Clock Signal (CK as Reference Signal)
Symbol
Min
tRPST 0.4
Symbol DDR 400A (2.5-3-3)
Min
tRPST 0.4
Obtain the parameters and settings from the Configuration page.
Pre-condition the scope setting. Verify the actual DUT speed against the user speed selection at
the Setup page.
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
DDR 333 DDR 266
Max Min Max
0.6 0.4 0.6
DDR 400B (3-3-3)
Max Min Max
0.6 0.4 0.6
DDR1 Compliance Testing Methods of Implementation
DDR 200 Units
Min Max
0.4 0.6 tCK
DDR 400C (3-4-4) Units
Min Max
0.4 0.6 tCK
Notes
33
Notes
33