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9
Data Mask Timing (DMT) Tests
PASS Condition
The measured time interval between the data or data mask (DQ/DM) hold time to the respective DQS
crossing point should be within the specification limit.
Measurement Algorithm
1
2
3
4
5
6
7
8
9
10 After obtaining the Edge number for the respective signal, begin the tDH(base) measurement bit
11 Continue the measurement until the last bit (for example, until a tristate happens, which
12 The DQS-DQ timing measurement compares the rising edge (DQ rising, for instance Vil_dc
13 Within the data burst, measure each bit, for instance rising and falling edge of the DQS-DQ.
14 Once all bits are validated, assign marker A for the clock signal while marker B for the data signal,
15 Measure delta of marker A and marker B and this will be the test result.
16 Compare the test result against the compliance test limit.
Test References
See Table 11 - Electrical Characteristics and AC Timing, in the JEDEC Standard JESD79E.
140
Obtain the parameters and settings from the Configuration page.
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Chip Select (CS) option is only applicable if the user has selected "Yes" for the Verify Selected
Rank Only option in the Configuration page. It uses the CS-DQS for signal separation. Else, by
default, the DQS-DQ is used for signal separation.
Use the InfiniiScan feature with the Setup time and Hold time to find and capture the Read cycle.
If you have selected the CS option, skip the next step and go to step 9.
Search for the DQS preamble towards the left from the point where the Write cycle was previously
captured. The For loops, TEdge and Delta Time are used to search the preamble.
Once the preamble is located, call the "BinaryEdgeNormal" function to obtain the Edge number
of the rise/fall DQS crossing and the Vih_dc/Vil_dc DQ for the later TEdge measurement use. This
Edge number will be used to locate the point of interest on the specific signal.
by bit in the Write data burst. Begin at the 1st bit of the Write cycle, from the Write preamble.
indicates the end of a data burst for the respective Write cycle).
against associated DQS crossing) OR the falling edge (DQ falling, for instance Vih_dc against
associated DQS crossing).
Capture the worst case data each time a new value is measured.
for the worst case bit.
DDR1 Compliance Testing Methods of Implementation
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