Table of Contents
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10 The Histogram Window is required to cover the DQ signal from the tristate to the moment it
11 Setup the threshold value and measurement point for the DQ signal based on the histogram
12 Once all the points are obtained, proceed with the trigonometry calculation to find the point
13 Assign marker A for the clock signal crossing point while marker B for the data signal start to
14 Measure delta of marker A and marker B and this will be the test result.
15 Compare the test result against the compliance test limit.
Test References
See Table 11 - Electrical Characteristics and AC Timing, in the JEDEC Standard JESD79E.
DDR1 Compliance Testing Methods of Implementation
starts to drive high/low state.
result.
where the DQ starts to transit from tristate to the time when it start to drive the signal high/low.
drive.
Data Strobe Timing (DST) Tests
7
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