Tac, Dq Output Access Time From Ck/Ck# - Test Method Of Implementation; Signals Of Interest; Test Definition Notes From The Specification - Keysight U7233A Testing Notes

tAC, DQ Output Access Time from CK/CK# - Test Method of Implementation

The purpose of this test is to verify that the time interval from data output (DQ Rising and Falling
Edge) access time to the nearest rising or falling edge of the clock must be within the conformance
limit as specified in the JEDEC Standard JESD79E.
There is tAC(min) and tAC(max) as shown in
the minimum value is at negative while the maximum is at positive.
Figure 38

Signals of Interest

Based on the test definition (Read cycle only):
•
•
Signals required to perform the test on the oscilloscope:
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•
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Optional signal required to separate the signals for the different Ranks:
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Test Definition Notes from the Specification

Table 49 Electrical Characteristics and AC Timing
AC Characteristics - Parameter
DQ output access time from CK/CK
DDR1 Compliance Testing Methods of Implementation
DQ Output Access Time from CK/CK#
Data Signal (DQ as Pin Under Test Signal)
Clock Signal (CK as Reference Signal)
Data Signal (DQ as Pin Under Test Signal)
Data Strobe Signal (DQS as Supporting Signal)
Clock Signal (CK as Reference Signal)
Chip Select Signal (CS as additional signal, which requires an additional channel
Symbol
Min
tAC -0.70
Figure 39. From the specification, you can observe that
DDR 333 DDR 266
Max Min Max
+0.70 -0.75 +0.75
Clock Timing (CT) Tests
DDR 200 Units
Min Max
-0.8 +0.8 ns
8
Notes
121