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3
Single-Ended Signals AC Input Parameters Tests
V
Test Method of Implementation
IH(DC)
V
IH(DC)
level voltage value of the test signal within a valid sampling window is within the conformance limits
of the V
The default value of V
change this value.
Table 8
Speed
V
V
V
Figure 9
Signals of Interest
Based on the test definition (Write cycle only):
•
•
•
•
44
- Minimum DC Input Logic High. The purpose of this test is to verify that the minimum high
value specified in the JEDEC Standard JESD79E.
IH(DC)
V
REF,
DD
The defaul t value of V
REF,
DDR 200, 266, 333
2.50 V
DDQ
2.50 V
DD
1.25 V
REF
V
Test - Minimum DC Input Logic High in Infiniium oscilloscope
IH(DC)
Data Signal
Data Strobe Signal OR
Address Signal OR (Note: Address is not included in the Low Power)
Control Signal OR
and V
is as shown in
Table
DDQ
V
and V
DD
DDQ
DDR 400
2.60 V
2.60 V
1.30 V
DDR1 Compliance Testing Methods of Implementation
8. However, users have the flexibility to
Low Power
1.80 V
1.80 V
0.90 V
.
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