Twpst, Write Postamble - Test Method Of Implementation; Signals Of Interest; Test Definition Notes From The Specification; Pass Condition - Keysight U7233A Testing Notes

7 Data Strobe Timing (DST) Tests

tWPST, Write Postamble - Test Method of Implementation

The purpose of this test is to verify that the time when the DQS is no longer driving (from high/low
state to high impedance) from the last DQS signal crossing (last bit of the write data burst) for the
Write cycle, is within the conformance limit as specified in the JEDEC Standard JESD79E.

Signals of Interest

Based on the test definition (Write cycle only):
•
Signals required to perform the test on the oscilloscope:
•
•
•
Optional signal required to separate the signals for the different Ranks:
•

Test Definition Notes from the Specification

Table 44 Electrical Characteristics and AC Timing
AC Characteristics Parameter
Write postamble
AC Characteristics Parameter
Write postamble
NOTE 16: The maximum limit for this parameter is not device limit. The device will operate with
greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.

PASS Condition

The measured time interval between the last DQS signal crossing point and the point where the DQS
starts to transit from high/low state to high impedance should be within the specification limit.

Measurement Algorithm

1
2
3
4
108
Data Strobe Signal (DQS as Pin Under Test Signal)
Data Strobe Signal (DQS as Pin Under Test Signal)
Data Signal (DQ as Supporting Signal)
Clock Signal (CK as Reference Signal)
Chip Select Signal (CS as additional signal, which requires an additional channel)
Obtain the parameters and settings from the Configuration page.
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Symbol DDR 333
Min Max Min
tWPST 0.40 0.60 0.40
Symbol DDR 400A
(2.5-3-3)
Min Max Min
tWPST 0.40 0.60 0.40
DDR1 Compliance Testing Methods of Implementation
DDR 266 DDR 200
Max Min Max
0.60 0.40 0.60
DDR 400B DDR 400C
(3-3-3) (3-4-4)
Max Min Max
0.60 0.40 0.60
Units Notes
tCK 16
Units Notes
tCK 16