Keysight U7233A Testing Notes page 4

Ddr1 compliance test application
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Table 1
Cycles and Signals
NOTE: 1 = Single Ended probing; 2 = Differential probing; 3 = 2 x Single Ended probing
Read Write DQ DQS CK ADD Ctrl
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tWPST
tWPRE
tRPRE
tRPST
tDS(base)
tDH(base)
tIS(base)
tIH(base)
High State
Ringing
Low State
Ringing
tJIT(per)
tJIT(cc)
tERR(nper)
tJIT(duty)
4
Data
DQ DQS CK ADD Ctrl
Mask
Ctrl
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
2
2
2
2
DDR1 Compliance Testing Methods of Implementation
Data
CS#
Mask
Ctrl
1,2
1,2

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