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Measurement Algorithm
Example input test signal: Frequency: 1 KHz, Number of cycles acquired: 202.
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Test References
See Table 11 - Electrical Characteristics and AC Timing and Table 12 - AC Timing Variations for DDR
333, DDR 266 and DDR 200 Devices, in the JEDEC Standard JESD79E.
DDR1 Compliance Testing Methods of Implementation
This measurement measures a sliding "window" of 200 cycles.
Calculate the average period value for periods 1-200, 2-201 and 3-202.
Check the results for the smallest and largest values (worst case values).
Compare the test results against the compliance test limits.
Clock Timing (CT) Tests
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