High State Ringing Tests Method Of Implementation; Signals Of Interest - Keysight U7233A Testing Notes

12 Advanced Debug Mode High-Low State Ringing Tests

High State Ringing Tests Method of Implementation

The Advanced Debug Mode Ringing test can be divided into two sub-tests. One of them is the High
State Ringing test. There is no available specification for this test in the JEDEC Standard JESD79E
specifications. The ringing debug test is definable by the customers to capture the glitch of interest
for the logic high state section in a test signal for evaluation purposes. The purpose of this test is to
automate all the required setup procedures, particularly the InfiniiScan RUNT mode setup, to
capture the ringing section of a test signal. Users are required to customize the threshold value in the
Configure tab to capture the specific RUNT signals. The expected results are signals captured on the
screen that fulfill the InfiniiScan RUNT criteria. There is a pulse in the captured signal that passes
through two voltage level threshold but not the third.
Figure 51

Signals of Interest

Based on the test definition (Write cycle only):
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Signals required to perform the test on the oscilloscope:
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High State Ringing Test
Data Signals OR
Data Strobe Signals OR
Address Signals OR
Control Signal OR
Data Mask Control Signals
Data Signal (DQ as Pin Under Test Signal)
Clock Signal - CK is required to perform pre-test to verify the DUT speed against the user's speed
grade selection
DDR1 Compliance Testing Methods of Implementation