Tih(Base) - Address And Control Input Hold Time - Test Method Of Implementation; Signals Of Interest; Test Definition Notes From The Specification; Pass Condition - Keysight U7233A Testing Notes

tIH(base) - Address and Control Input Hold Time - Test Method of Implementation

The purpose of this test is to verify that the time interval from the address or control (rising or falling
edge) hold time to the associated clock crossing edge is within the conformance limits as specified in
the JEDEC Standard JESD79E.

Signals of Interest

Based on the test definition (Read cycle only):
•
•
Signals required to perform the test on the oscilloscope:
•
•

Test Definition Notes from the Specification

Table 62 Electrical Characteristics and AC Timing
AC Characteristics Parameter
Address and Control input hold time (fast slew rate)
Address and Control input hold time (slow slew
rate)
AC Characteristics Parameter
Address and Control input setup time (fast slew
rate)
Address and Control input setup time (slow slew
rate)
NOTE i: A derating factor will be used to increase tIS and tIH in the case where the input slew rate is
below 0.5 V/ns. The input slew rate is based on the lesser of the slew rates determined by either
VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. A derating factor applies to
speed bins DDR 200, DDR 266 and DDR 333.
NOTE 19: For command/address input slew rate ≥ 1.0 V/ns.
NOTE 20: For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
NOTE 21: For CK and CK#, slew rate ≥ 1.0 V/ns (single-ended).
NOTE 22: These parameters guarantee device timing, but they are not necessarily tested on each
device. They may be guaranteed by device design or tester correlation.
NOTE 23: Slew Rate is measured between VOH(AC) and VOL(AC).

PASS Condition

The measured time interval between the address/control hold time and the respective clock crossing
point should be within the specification limit.
DDR1 Compliance Testing Methods of Implementation
Address and Control Signal (as Pin Under Test Signal)
Clock Signal (CK as Reference Signal)
Address and Control Signal (as Pin Under Test Signal)
Clock Signal (CK as Reference Signal)
Symbol
Min
tIH 0.75
tIH 0.80
Symbol DDR 400A (2.5-3-3)
Min
tIH 0.60
tIH 0.70
DDR 333 DDR 266
Max Min Max
0.9
1.0
DDR 400B (3-3-3)
Max Min Max
0.60
0.70
Command and Address Timing (CAT) Tests
DDR 200 Units
Min Max
1.1 ns
1.1 ns
DDR 400C (3-4-4) Units
Min Max
0.60 ns
0.70 ns
10
Notes
19,
21-23, i
20-23, j
Notes
19,
21-23
20-23
147