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V
Test Method of Implementation
IH(AC)
V
IH
V
IH(AC)
level voltage value of the test signal within a valid sampling window is greater than the conformance
lower limit of the V
measured value must fall in between the conformance limits.
The default value of V
Table
Table 5
Speed
V
V
Figure 8
Signals of Interest
Based on the test definition (Write cycle only):
•
•
DDR1 Compliance Testing Methods of Implementation
Input Logic High Test can be divided into two sub tests - V
- Maximum AC Input Logic High. The purpose of this test is to verify that the maximum high
value specified in the JEDEC Standard JESD79E. For low power devices, the
IH(AC)
and V
REF
5. However, users have the flexibility to change this value.
The defaul t value of V
REF
DDR 200, 266, 333
2.50 V
DDQ
1.25 V
REF
V
Test - Maximum AC Input Logic High in Infiniium oscilloscope
IH(AC)
Data Signal
Data Strobe Signal OR
Single-Ended Signals AC Input Parameters Tests
which directly affects the conformance lower limit is as shown in
DDQ
and V
DDQ
DDR 400
2.60 V
1.30 V
test and V
test.
IH(AC)
IH(DC)
Low Power
1.80 V
0.90 V
.
3
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