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Clock Timing (CT) Tests
8
14 Once all bits are validated, assign marker A for the clock signal while marker B for the data signal,
for the worst case bit.
15 Measure delta of marker A and marker B and this will be the test result.
16 Compare the test result against the compliance test limit.
Test References
See Table 11 - Electrical Characteristics and AC Timing and Table 12 - AC Timing Variations For DDR
333, DDR 266 and DDR 200 Devices, in the JEDEC Standard JESD79E.
DDR1 Compliance Testing Methods of Implementation
127
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