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•
Signals required to perform the test on the oscilloscope:
•
•
•
* Pin Under Test signal can be either one of the signals under the test definition.
Test Definition Notes from the Specification
Table 25
AC Overshoot/Undershoot Specification for Address and Control Pins
Parameter
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
The area between the overshoot signal and VDD must be less than or equal to
The area between the undershoot signal and GND must be less than or equal to
Table 26
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
The area between the overshoot signal and VDD must be less than or equal to
The area between the undershoot signal and GND must be less than or equal to
PASS Condition
The measured minimum voltage value for the test signal can be less than or equal to the maximum
undershoot value.
The calculated undershoot area value can be less than or equal to the maximum undershoot area
allowed.
Measurement Algorithm
1
2
3
4
5
DDR1 Compliance Testing Methods of Implementation
Data Mask Control Signals
Data Signal (DQ as Pin Under Test Signal)*
Data Strobe Signal (DQS as Supporting Signal)
Clock Signal - CK is required to perform pre-test to verify the DUT speed against user's speed
grade selection
Set the number of sampling points to 2M samples.
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Calculate initial time scale value based on the number of sampling points.
Obtain sample or acquire signal data and perform signal conditioning to maximize the screen
resolution (vertical scale adjustment).
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Single-Ended Signals Overshoot/Undershoot Tests
Specification
DDR 333
TBD
TBD
TBD
TBD
Specification
DDR 333
TBD
TBD
TBD
TBD
5
DDR 200/266
1.5 V
1.5 V
4.5 V-ns
4.5 V-ns
DDR 200/266
1.2 V
1.2 V
2.4 V-ns
2.4 V-ns
69
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