Serial Flash Memory Layout - Intel Agilex Series Configuration User Manual

This configuration scheme includes the following steps:
1. In the Intel Quartus Prime Programmer, select the JTAG programming mode and initiate programming by clicking Start.
2. The Programmer drives
3. The programmer first configures the SDM with configuration firmware. Then, the SDM drives configuration data from the
programmer to the AS x4 flash device using SDM_IOs.
4. If your current
after successful programming of the flash device, set the
the device.
The Intel Quartus Prime Programmer interfaces to the SDM device through JTAG interface and programs the serial flash
device.

3.2.7. Serial Flash Memory Layout

Serial flash devices store the configuration data in sections.
The following diagram illustrates sections of a non-HPS Intel Agilex configuration data mapping in a serial flash device. Refer
to Intel Agilex SoC FPGA Bitstream Sections of the HPS Technical Reference Manual for more information about flash memory
layout for HPS devices.
Figure 45. Serial Flash Memory Layout Diagram
Intel ® Agilex ™ Configuration User Guide
114
configuration data to the board using the JTAG header connection.
.jic
pins are not set to AS fast or normal mode in order to configure the Intel Agilex device in AS mode
MSEL
Start Address 32' d 0
32' d 512k
32'1024k
32' d 1536k
32' d 2048k
Dynamic Section (I/O Configuration)
Dynamic Section ( FPGA Core Configuration)
End Address
(Design dependent)
pins to either AS fast or AS normal mode and power cycle
MSEL
Firmware Section
Firmware section
Firmware Section
is dependent on
the Quartus Prime
Firmware Section
Programmer version
Firmware Section
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
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