Layout Review Checklist; Processor And System Bus; Agtl+ Signals - Intel Pentium 4 Design Manual

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Layout Review Checklist

This checklist highlights design considerations that should be reviewed prior to manufacturing a
motherboard that implements an Intel 850 chipset. The items contained within this checklist
attempt to address important connections to these devices and any critical supporting circuitry.
This is not a complete list and does not guarantee that a design will function properly. Beyond the
items contained in the following text, refer to the most recent version of the design guide for more
detailed instructions on designing a motherboard.
16.1

Processor and System Bus

16.1.1

AGTL+ Signals

This section covers the address, Data, DSTBn/p#, ADSTBn/p# and common clock signals. Refer
to the processor datasheet for a system bus list, signal types and definitions.
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® ®
Intel Pentium 4 Processor / Intel
Recommendations
• Trace width recommendation is 7 mils with
13 mil edge-to-edge spacing for all signals.
Trace spacing can be approximately 5 mils
within pin field.
• Processor clock differential pairs should
have a minimum of 20mil spacing from
other signals.
• Data signal (D[63:0], and DBI[3:0]#) length
should be 2 inches – 10 inches pin-to-pin.
Data signals of the same source
synchronous group should be routed to the
same pad-to-pad length ±100 mils. Length
must be added to the motherboard to
compensate for package length differences.
• A strobe and its complement (DSTBP[3:0]#
and DSTBN[3:0]#) should be routed within
±25 mils of the same pad-to-pad length
®
850 Chipset Family Platform Design Guide
Layout Review Checklist
Reason/Impact/Documentation
• Refer to Section 5.3.
• The length compensation will result in
minimizing the source synchronous skew
that exists on the system bus. Without trace
matching and length compensation flight
times between the data signals and the
strobes will result in inequity between the
setup and hold times.
• Refer to Chapter 2.
• The impact of this recommendation causes
the strobe to be received closer to the
center of the data pulse, which results in
reasonably comparable setup and hold
times. It is recommended to simulate skew
in order to determine the length that best
centers the strobe for a given system.
• Refer to Chapter 2.
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