Table of Contents
Advertisement
11.0
Serial ATA (SATA) Interface
11.1
SATA Interface
The EP80579 contains two SATA ports capable of independent DMA operation. The
SATA interface supports data transfer rates up to 1.5 Gb/s or 3.0 Gb/s per port.
11.1.1
General Routing and Placement
Use the following general routing and placement guidelines when laying out a new
design (see
• Serial ATA signals must be ground referenced, preferred routing on layers 3 and 8.
If changing reference plane is completely unavoidable (i.e. ground reference to
power reference), proper placement of stitching caps can minimize the adverse
effects on EMI and signal quality performance caused by reference plan change.
Stitching capacitors are small-valued capacitors (1uF or lower in value) that bridge
the power and ground planes close to where a high-speed signal changes layers.
Stitching caps provide a high frequency current return path between different
reference planes. They minimize the impedance discontinuity and current loop area
that crossing different reference planes created. Max number allowable for SATA to
change reference plane is one.
• Route all traces over continuous GND planes, with no interruptions. Avoid crossing
over anti-etch if at all possible. Any discontinuity or split in the ground plane can
cause signal reflections and must be avoided.
• Minimize layer changes. Use a maximum of 2 vias per SATA trace for microstrip or
a maximum of 2 vias for stripline. Via count includes thru-hole connector as an
effective via. Use a maximum of six vias for stripline in order to connect to the AC
decoupling capacitors. If a layer change is necessary, ensure that trace matching
for either the transmit or receive pair occurs within the same layer. Recommend to
use SATA vias as small as possible.
• Do not route SATA traces under power connectors, other interface connectors,
crystals, oscillators, clock synthesizers, magnetic devices or IC's that use and/or
duplicate clocks.
• Avoid stubs (e.g., usually introduced by test points) whenever possible. Utilize vias
and connector pads as test points instead.
• It can be helpful for testability to route the Tx and Rx pairs for a given port on the
same layer and close to each other to help ensure the pairs share similar signaling
characteristics. If the groups of traces are similar, a measure of Rx pair layout
quality can be approximated by using the results from actively testing the Tx pair's
signal quality.
• Do not serpentine to match Rx and Tx traces; there is NO requirement to match Rx
and Tx traces. In addition, DO NOT serpentine to meet minimum length guidelines
on Rx and Tx.
Note:
The minimum length must be met. That minimizes our Max peak to peak differential
voltage (for Gen 2). Properly placing a SATA connector (not too close to the EP80579)
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
152
®
Intel
EP80579 Integrated Processor Product Line—Serial ATA (SATA) Interface
Figure
98):
May 2010
Order Number: 320068-005US
Advertisement
Table of Contents
