Figure 12-36: Timing Chart Of Interrupt Request Signal Output In Delay Mode (1/2) - NEC V850E/CA1 ATOMIC Preliminary User's Manual

(c) Transmission/reception completion interrupt request signals (INTCSI0, INTCSI1)
INTCSI0n is set (1) upon completion of data transmission/reception.
Caution: The delay mode (CSIT bit = 1) is valid only in the master mode (bits CKS2 to CKS0 of
the CSICn register are not 111B). The delay mode cannot be set when the slave mode
is set (bits CKS2 to CKS0 = 111B).

Figure 12-36: Timing Chart of Interrupt Request Signal Output in Delay Mode (1/2)

(a) When CKP bit = 0, DAP bit = 0
(input/output)
SCKn (input/output)
SIn (input)
SOn (output)
Reg_R/W
INTCSIn
interrupt
CSOT bit
Remarks: 1. n = 0, 1
2. Reg_R/W:Internal signal. This signal indicates that receive data buffer register (SIRBn/
SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was performed.
Chapter 12 Serial Interface Function
DI7 DI6
DO7 DO6
Preliminary User's Manual U14913EE1V0UM00
DI5 DI4 DI3
DO5 DO4 DO3
DI2 DI1 DI0
DO2 DO1 DO0
Delay
357