Configuration Of Power-On-Clear Circuit; Operation Of Power-On-Clear Circuit - NEC mPD78F0730 Preliminary User's Manual

16.2 Configuration of Power-on-Clear Circuit

The block diagram of the power-on-clear circuit is shown in Figure 16-1.

16.3 Operation of Power-on-Clear Circuit

In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
• An internal reset signal is generated on power application.
detection voltage (V
• The supply voltage (V
internal reset signal is generated. It is released when V
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is
shown below.
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CHAPTER 16 POWER-ON-CLEAR CIRCUIT
Figure 16-1. Block Diagram of Power-on-Clear Circuit
V
DD
Reference
voltage
source
= 2.7 V ±0.2 V), the reset status is released.
DDPOC
) and detection voltage (V
DD
Preliminary User's Manual U19014EJ1V0UD
V
DD
+
−
When the supply voltage (V
= 1.59 V ±0.15 V) are compared. When V
POC
≥ V
.
DD DDPOC
Internal reset signal
) exceeds the
DD
< V
DD
, the
POC
431