Configuration Of Power-On-Clear Circuit; Operation Of Power-On-Clear Circuit - NEC 78K0S/KA1+ User Manual

15.2 Configuration of Power-on-Clear Circuit

The block diagram of the power-on-clear circuit is shown in Figure 15-1.
V
DD

15.3 Operation of Power-on-Clear Circuit

In the power-on-clear circuit, the supply voltage (V
and an internal reset signal is generated when V
Figure 15-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit
Supply voltage (V )
DD
POC detection voltage
(V = 2.1 V ±0.1 V)
POC
Internal reset signal
246
CHAPTER 15 POWER-ON-CLEAR CIRCUIT
Figure 15-1. Block Diagram of Power-on-Clear Circuit
V
DD
+
−
Reference
voltage
source
) and detection voltage (V
DD
< V
DD POC
User's Manual U16898EJ3V0UD
Internal reset signal
POC
, and an internal reset is released when V
= 2.1 V ±0.1 V) are compared,
≥ V .
DD POC
Time