Pin Status When Internal Rom, Internal Ram, Or Peripheral I/O Is Accessed; Pin Status In Each Operation Mode - NEC V850ES/SA2 UPD703201 Manual

Bus Control Pin
AD0 to AD15
A0 to A15
Note
A16 to A23
WAIT
CLKOUT
CS0 to CS3
WR0, WR1
RD
HLDRQ
HLDAK
Note A16 to A21 in the V850ES/SA2
5.2.1

Pin status when internal ROM, internal RAM, or peripheral I/O is accessed

Table 5-3. Pin Status When Internal ROM, Internal RAM, or Peripheral I/O Is Accessed
Access Destination
D0 to D15
A0 to A15
A16 to A23
Note When a peripheral I/O is accessed, the address bus outputs the address of the internal peripheral I/O that is
accessed.
5.2.2

Pin status in each operation mode

For the pin status of the V850ES/SA2 and V850ES/SA3 in each operation mode, refer to 2.2 Pin Status.
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CHAPTER 5 BUS CONTROL FUNCTION
Table 5-2. External Control Pins (Separate Bus)
Alternate-Function Pin I/O
PDL0 to PDL15 I/O
P90 to P915 Output
PDH0 to PDH7 Output
PCM0 Input
PCM1 Output
PCS0 to PCS3 Output
PCT0, PCT1 Output
PCT4 Output
PCM3 Input
PCM2 Output
Address Bus
Undefined
Undefined
Note
Preliminary User's Manual U15905EJ1V0UD
Function
Data bus
Address bus
Address bus
External wait control
Internal system clock
Chip select
Write strobe signal
Read strobe signal
Bus hold control
Data Bus Control Signal
Hi-Z Inactive
Hi-Z Inactive
Hi-Z Inactive