Watchdog Timer Operation In Stop Mode (When "Low-Speed Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte) - NEC 78K0S/KA1+ Preliminary User's Manual

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9.4.3
The watchdog timer stops counting during STOP instruction execution regardless of whether the clock to peripheral
hardware or low-speed Ring-OSC clock is being used.
(1) When the watchdog timer operation clock is the clock to peripheral hardware (f
instruction is executed
When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,
operation stops for 8 clocks of the low-speed Ring-OSC clock (after waiting for the oscillation stabilization time set
by the oscillation stabilization time select register (OSTS) after operation stops in the case of crystal/ceramic
oscillation) and then counting is started again using the operation clock before the operation was stopped. At this
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time, the counter is not cleared to 0 but holds its value.
CPU operation
Watchdog timer
Watchdog timer operation in STOP mode (when "low-speed Ring-OSC can be stopped by software" is
selected by option byte)
Figure 9-6. Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware)
<1> CPU clock: Crystal/ceramic oscillation clock
Normal
operation STOP
f
CPU
Oscillation stopped
Operating
<2> CPU clock: High-speed Ring-OSC clock or external clock input
Normal
operation
CPU operation
f
CPU
Watchdog timer
Operating
CHAPTER 9 WATCHDOG TIMER
Operation
stopped Oscillation stabilization time
(8/f )
RL
Oscillation stabilization time
(set by OSTS register)
Operation stopped
Operation
STOP
stopped
(8/f )
RL
Oscillation stopped
Operation stopped
Preliminary User's Manual U16898EJ1V0UD
) when the STOP
XP
Normal operation
Operating
Normal operation
Operating
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