Interrupt Mask; Interrupt Vector - Epson S1C63358 Technical Manual

4.15.2 Interrupt mask

The interrupt factor flags can be masked by the corresponding interrupt mask registers.
The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is
written to them, and masked (interrupt inhibited) when "0" is written to them.
At initial reset, the interrupt mask register is set to "0".
Table 4.15.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags.

4.15.3 Interrupt vector

When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program
being executed is terminated, the interrupt processing is executed in the following order.
1 The content of the flag register is evacuated, then the I flag is reset.
2 The address data (value of program counter) of the program to be executed next is saved in the stack
area (RAM).
3 The interrupt request causes the value of the interrupt vector (0100H–010EH) to be set in the program
counter.
4 The program at the specified address is executed (execution of interrupt processing routine by
software).
Table 4.15.3.1 shows the correspondence of interrupt requests and interrupt vectors.
The four low-order bits of the program counter are indirectly addressed through the interrupt request.
S1C63358 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.15.2.1 Interrupt mask registers and interrupt factor flags
Interrupt mask register
( FFE2H•D1 )
EIPT1
( FFE2H•D0 )
EIPT0
( FFE3H•D0 )
EISIF
( FFE4H•D0 )
EIK0
( FFE5H•D0 )
EIK1
( FFE5H•D1 )
EIK2
( FFE 6H•D3 )
EIT3
( FFE6H•D2 )
EIT2
( FFE6H•D1 )
EIT1
( FFE6H•D0 )
EIT0
( FFE7H•D0 )
EIAD
Table 4.15.3.1 Interrupt request and interrupt vectors
Interrupt vector
0100H Watchdog timer
0104H Programmable timer
0106H Serial interface
0108H K00–K03 input
010AH K10–K13 input, K20 input
010CH Clock timer
010EH A/D converter
Interrupt factor flag
( FFF2H•D1 )
IPT1
( FFF2H•D0 )
IPT0
( FFF3H•D0 )
ISIF
( FFF4H•D0 )
IK0
( FFF5H•D0 )
IK1
( FFF5H•D1 )
IK2
( FFF6H•D3 )
IT3
( FFF6H•D2 )
IT2
( FFF6H•D1 )
IT1
( FFF6H•D0 )
IT0
( FFF7H•D0 )
IAD
Interrupt factor Priority
High
Low
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