Sp Operation When An Interrupt Or Exception Occurs - Epson S1C33 Series Core Manual

2.4.5 SP Operation when an Interrupt or Exception Occurs

If an interrupt or software exception resulting from the int instruction occurs, the processor enters an exception
handling process.
The processor pushes the contents of the PC and PSR onto the stack indicated by the SP before branching to
the relevant interrupt handler routine. This is to save the contents of the two registers before they are altered by
interrupt or exception handling. The PC and PSR data is pushed onto the stack as shown in the diagram below.
For returning from the handler routine, the reti instruction is used to pop the contents of the PC and PSR off the
stack. In the reti instruction, unlike in ordinary pop operation, the PC and PSR are read out of the stack in that
order, and the SP address is altered as shown in the diagram below.
SP operation when an interrupt occurred
(1) SP = SP - 4
(2) PC → [SP]
(3) SP = SP - 4
(4) PSR → [SP]
SP
SP operation when the reti instruction is executed
(1) [SP + 4] → PC
(2) [SP] → PSR
(3) SP = SP + 8
SP
S1C33 FAMILY C33 PE CORE MANUAL
0xFFFFFFFF
31 0
0x00000000
Figure 2.4.5.1 SP and Stack (5)
0xFFFFFFFF
31 0
PC
PSR
0x00000000
Figure 2.4.5.2 SP and Stack (6)
EPSON
0xFFFFFFFF
31
PC
SP = SP - 8
PSR
0x00000000
0xFFFFFFFF
31
SP = SP + 8
PC
PSR
0x00000000
2 REGISTERS
0
0
9