Data Transfer Instructions (Between Stack And Register) - Epson S5U1C17001C Manual

8.6.4 Data Transfer instructions (between Stack and register)

Types and functions of extended instructions
Extended instruction
%rd,[%sp+imm20] %rd ← B[%sp+imm20] (with sign extension)
sld.b
%rd,[%sp+imm20] %rd ← B[%sp+imm20] (with zero extension)
sld.ub
%rd,[%sp+imm20] %rd ← W[%sp+imm20]
sld
%rd,[%sp+imm20] %rd ← A[%sp+imm20](23:0) , ignored ← A[%sp+imm20](31:24)
sld.a
[%sp+imm20],%rs B[%sp+imm20] ← %rs(7:0)
sld.b
[%sp+imm20],%rs W[%sp+imm20] ← %rs(15:0)
sld
[%sp+imm20],%rs A[%sp+imm20](23:0) ← %rs(23:0) , A[%sp+imm20](31:24) ← 0
sld.a
%rd,[%sp+imm24] %rd ← B[%sp+imm24] (with sign extension)
xld.b
%rd,[%sp+imm24] %rd ← B[%sp+imm24] (with zero extension)
xld.ub
%rd,[%sp+imm24] %rd ← W[%sp+imm24]
xld
%rd,[%sp+imm24] %rd ← A[%sp+imm24](23:0) , ignored ← A[%sp+imm24](31:24)
xld.a
[%sp+imm24],%rs B[%sp+imm24] ← %rs(7:0)
xld.b
[%sp+imm24],%rs W[%sp+imm24] ← %rs(15:0)
xld
[%sp+imm24],%rs A[%sp+imm24](23:0) ← %rs(23:0) , A[%sp+imm20](31:24) ← 0
xld.a
These extended instructions allow you to directly specify a displacement of up to 20 bits/24 bits. Specification
of imm20/imm24 can be omitted.
Basic instructions after expansion
Expanded into the ld.b instruction
sld.b, xld.b
Expanded into the ld.ub instruction
sld.ub, xld.ub
Expanded into the ld instruction
sld, xld
Expanded into the ld.a instruction
sld.a, xld.a
Expansion formats
If imm20/imm24 is omitted, the as assembler assumes that [%sp+0x0] is specified as it expands the
instruction.
(1) sOP
%rd,[%sp+imm20]
sOP [%sp+imm20],%rs
Example: sld.a
%rd,[%sp+imm20]
imm20 ≤ 0x7f
ld.a %rd,[%sp+imm20(6:0)]
(2) xOP
%rd,[%sp+imm24]
xOP [%sp+imm24],%rs
Example: xld.a
%rd,[%sp+imm24]
imm24 ≤ 0x7f
ld.a %rd,[%sp+imm24(6:0)]
S5U1C17001C ManUal
(C COMPilEr PaCkagE fOr S1C17 faMily) (Ver. 1.5.0)
function
(OP = ld.b, ld.ub, ld, ld.a)
(OP = ld.b, ld, ld.a)
0x7f < imm20
ext imm20(19:7)
ld.a %rd,[%sp+imm20(6:0)]
(OP = ld.b, ld.ub, ld, ld.a)
(OP = ld.b, ld, ld.a)
0x7f < imm24 ≤ 0xfffff
ext imm24(19:7)
ld.a %rd,[%sp+imm24(6:0)]
EPSOn
8 aSSEMBlEr
Expansion
0xfffff < imm24
ext imm24(23:20)
ext imm24(19:7)
ld.a %rd,[%sp+imm24(6:0)]
(1)
(1)
(1)
8
(1)
Assemblr
(1)
(1)
(1)
(2)
(2)
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8-17