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2.2.3 Oscillation detection circuit
With RESET = H, the oscillation detection circuit receives f
frequency is greater than a certain value, the oscillation output goes to L to clear the reset state. The time
required for f-V conversion depends on f
gives a delay for clearing the reset state from the RESET input going to H.
The oscillation detection circuit may sometimes not operate normally with the initial resetting due to the
circuit, depending on the method of making the power, you should utilize the initial resetting method by
the RESET pin.
2.2.4 Watchdog timer
The watchdog timer guards the CPU against an unexpected overrun. It uses the OSC1 clock as the source
oscillation frequency to perform the increment operation. If the watchdog timer fails to be reset in 3–4
seconds with f
= 32 kHz, the CPU will be initialized at initial reset.
OSC1
See Section 4.2, "Watchdog Timer", for details.
2.2.5 Initialization by initial reset
When the E0C6006 is initially reset, its internal registers are set as follows:
2.3 Test Input Pin (TEST)
This pin is used when IC is inspected for shipment.
During normal operation connect it to V
E0C6006 TECHNICAL MANUAL
, and is several milliseconds with f
OSC1
Table 2.2.5.1 Initial status
CPU Core
Name
Program counter step
Program counter page
New page pointer
Stack pointer
Index register X
Index register Y
Register pointer
General-purpose register A
General-purpose register B
Interrupt flag
Decimal flag
Zero flag
Carry flag
Peripheral Circuits
Name
RAM
Display memory
Other peripheral circuits
.
DD
EPSON
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
and makes a f-V conversion. If the OSC1
OSC1
Symbol
Bit size
Initial value
PCS
8
00H
PCP
4
1H
NPP
4
1H
SP
8
Undefined
X
8
Undefined
Y
8
Undefined
RP
4
Undefined
A
4
Undefined
B
4
Undefined
I
1
0
D
1
0
Z
1
Undefined
C
1
Undefined
Bit size
Initial value
128×4
Undefined
20×4
Undefined
∗
–
∗ See Section 4.1, "Memory Map".
= 32 kHz. This time
OSC1
7
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