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2 MEMORY AND OPERATIONS
2.5 Interrupts
The S1C6200/6200A can have up to 15 interrupt vectors. When used with peripheral circuits, these allow
internal and external interrupts to be processed easily. See Figure 2.5.3.1 through 2.5.3.4.
2.5.1 Interrupt vectors
The interrupt vectors are assigned to steps 1 to 15 in page 1 of each bank of the program memory. When an
interrupt occurs, the program jumps to the appropriate interrupt vector in the current bank.
The priority and linking of these vectors to actual outside events depends on the configuration of the
peripheral circuits and therefore is device-specific. This information can be found in the technical manuals
for the specific device.
2.5.2 I (interrupt) flag
The I (interrupt) flag enables or disables all interrupts.
When DI or RST F is used to reset the I flag, interrupts are disabled with that instruction step. When EI or
SET F is used to set the I flag, interrupts are enabled after the following instruction step. For example, to
return control from the interrupt subroutine to the main routine, the sequence EI, RET, does not enable
interrupts until after RET has been executed.
The I flag is reset to 0 (DI) on reset.
2.5.3 Operation during interrupt generation
When an interrupt is generated, the program is halted, the program counter (PCP and PCS) is stored on the
stack, the I flag is reset to DI mode and NPP is set to 1. The program then branches to the interrupt vector
corresponding to the interrupt request. Registers and flags are unaffected by an interrupt.
Register and flag data must be saved by the program since they are not automatically stored on the stack.
The I flag can be set to 1 (EI) within the interrupt subroutine, because nesting of multiple interrupts is
available.
If an interrupt is generated while the CPU is in HALT or SLP mode, the CPU is restarted and the interrupt
serviced. When the interrupt service routine is completed, the program resumes from the instruction
following the HALT or SLP.
<Differences between S1C6200 and S1C6200A>
In the S1C6200 and the S1C6200A, the time it takes to complete interrupt processing by hardware after the
Core CPU receives the interrupt request is different as follows:
a) During instruction execution
b) At HALT mode
c) During PSET instruction execution
12
Table 2.5.3.1 Required interrupt processing time
Item
12-cycle instruction execution
7-cycle instruction execution
5-cycle instruction execution
PSET + CALL
PSET + JP
EPSON
S1C6200A
S1C6200
(clock cycles)
(clock cycles)
12.5 to 24.5
13 to 25
12.5 to 19.5
13 to 20
12.5 to 17.5
13 to 18
14 to 15
14 to 15
12.5 to 24.5
13 to 25
12.5 to 22.5
13 to 23
S1C6200/6200A CORE CPU MANUAL
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