Clock Configuration Register; Power Save Configuration Registers; Table 8-9: Pclk Divide Selection; Vancouver Design Center - Epson S1D13505 Technical Manual

Page 110

8.2.5 Clock Configuration Register

Clock Configuration Register
REG[19h]
Reserved n/a
bit 7
bit 2
bits 1-0
PCLK Divide Select Bits [1:0]

8.2.6 Power Save Configuration Registers

Power Save Configuration Register
REG[1Ah]
Power Save
Status n/a
RO
bit 7
S1D13505
X23A-A-001-14
n/a n/a
Reserved
This bit must be set to 0.
Note
There must always be a source clock at CLKI.
MCLK Divide Select
When this bit = 1 the MCLK frequency is half of its source frequency.
When this bit = 0 the MCLK frequency is equal to its source frequency.
The MCLK frequency should always be set to the maximum frequency allowed by the DRAM; this
provides maximum performance and minimum overall system power consumption.
PCLK Divide Select Bits [1:0]
These bits select the MCLK: PCLK frequency ratio

Table 8-9: PCLK Divide Selection

00
01
10
11
See section on "Maximum MCLK:PCLK Frequency Ratios" for selection of clock ratios.
n/a n/a
Power Save Status
This is a read-only status bit.
This bit indicates the power-save state of the chip.
When this bit = 1, the panel has been powered down and the memory controller is either in self
refresh mode or is performing only
When this bit = 0, the chip is either powered up, in transition of powering up, or in transition of
powering down. See Section 15 Power Save Modes for details.
MCLK Divide
n/a
Select
MCLK: PCLK Frequency Ratio
1: 1
2: 1
3: 1
4: 1
Suspend
LCD Power
Refresh
Disable
Select Bit 1
CAS-before-RAS refresh cycles.
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Vancouver Design Center

PCLK Divide PCLK Divide
Select Bit 1 Select Bit 0
Suspend Software
Refresh Suspend
Select Bit 0 Mode Enable
Hardware Functional Specification
Issue Date: 01/02/02
RW
RW