Texas Instruments TMS320C28x Reference Manual page 93

What following list explains the steps shown in Figure 3−4:
1) Interrupt request sent to CPU. One of the following events occurs:
One of the pins INT1−INT14 is driven low by an external event, periph-
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eral or PIE interrupt request..
The CPU emulation logic sends to the CPU a signal for DLOGINT or
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RTOSINT.
One of the interrupts INT1−INT14, DLOGINT, and RTOSINT is initi-
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ated by way of the OR IFR instruction.
2) Set corresponding IFR flag bit. When the CPU detects a valid interrupt
in step 1, it sets and latches the corresponding flag in the interrupt flag reg-
ister (IFR). This flag stays latched even if the interrupt is not approved by
the CPU in step 3. The IFR is explained in detail in section 3.3.1.
3) Is the interrupt enabled in IER? Is the interrupt enabled by INTM bit?
The CPU approves the interrupt only if the following conditions are true:
The corresponding bit in the IER is 1.
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The INTM bit in ST1 is 0.
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Once an interrupt has been enabled and then approved by the CPU, no
other interrupts can be serviced until the CPU has begun executing the in-
terrupt service routine for the approved interrupt (step 13). The IER is de-
scribed in section 3.3.2. ST1 is described in section 2.4 on page 2-34.
4) Clear corresponding IFR bit. Immediately after the interrupt is approved,
its IFR bit is cleared. If the interrupt signal is kept low, the IFR register bit
will be set again. However, the interrupt is not immediately serviced again.
The CPU blocks new hardware interrupts until the interrupt service routine
(ISR) begins. In addition, the IER bit is cleared (in step 10) before the ISR
begins; therefore, an interrupt from the same source cannot disturb the
ISR until the IER bit is set again by the ISR.
5) Empty the pipeline. The CPU completes any instructions that have
reached or passed their decode 2 phase in the instruction pipeline. Any
instructions that have not reached this phase are flushed from the pipeline.
6) Increment and temporarily store PC. The PC is incremented by 1 or 2,
depending on the size of the current instruction. The result is the return
address, which is temporarily saved in an internal hold register. During the
automatic context save (step 9), the return address is pushed onto the
stack.
Standard Operation for Maskable Interrupts
CPU Interrupts and Reset 3-13