Texas Instruments TMS320C28x Reference Manual page 673

Glossary
N
O
N (negative flag) bit: A bit in status register ST0 that indicates whether the
result of a calculation is a negative number (N = 1). N is set to match the
MSB of the result.
nested interrupt: An interrupt that occurs within an interrupt service routine.
NMI: A hardware interrupt that is nonmaskable, like reset (RS), but does not
reset the CPU. NMI simply forces the CPU to execute its interrupt service
routine.
nonmaskable interrupt: An interrupt that cannot be blocked by software
and is approved by the CPU immediately. See also maskable interrupt.
offset branch: A branch that uses a specified or generated offset value to
jump to an address relative to the current position of the program counter
(PC). See also absolute branch.
opcode: This document uses opcode to mean the complete code for an in-
struction. Thus, an opcode includes the binary sequence for the instruc-
tion type and the binary sequence and/or constant in which the operands
are encoded.
operand : This document uses operand to mean one of the values entered
after the instruction mnemonic and separated by commas (or for a shift
operand, separated by the symbol <<). For example, in the CLRC INTM
instruction, CLRC is the mnemonic and INTM is the operand.
operation: 1) A defined action; namely, the act of obtaining a result from one
or more operands in accordance with a rule that completely specifies the
result of any permitted combination of operands. 2) The set of such acts
specified by a rule, or the rule itself. 3) The act specified by a single com-
puter instruction. 4) A program step undertaken or executed by a com-
puter; for example, addition, multiplication, extraction, comparison, shift,
transfer, etc. 5) The specific action performed by a logic element.
OVC: See overflow counter (OVC).
OVM: See overflow mode (OVM) bit.