Texas Instruments TMS320C28x Reference Manual page 238

CMPL ACC,P << PM
SYNTAX OPTIONS
CMPL ACC,P << PM
Operands ACC
P
<<PM
Description
Flags N
and
Modes
Z
C
PM
Repeat
Example
; Compare the following (VarA − VarB >> 4):
MOVL
SPM
MOVL
CMPL
1111 1111 0101 1001
Accumulator register
Product register
Product shift mode
The content of the ACC register is compared with the content of the P register,
shifted by the amount specified by the product shift mode (PM). The status
flag bits are set according to the result of (ACC −[ P << PM]). The content of the
ACC register and the P register are left unchanged:
Modify flags on (ACC − [P << PM]);
If the result of the operation is negative, then N is set; otherwise it is cleared.
The CMPL instruction assumes infinite precision when it determines the sign
of the result. For example, consider the subtraction 0x8000 0000 − 0x0000
0001. If the precision were limited to 32 bits, the result would cause an
overflow to the positive number 0x7FFF FFFF and N would be cleared.
However, because the CMPL instruction assumes infinite precision, it would
set N to indicate that 0x8000 0000 − 0x0000 0001 actually results in a
negative number.
The comparison is tested for a zero condition. The zero flag bit is set if the
operation (AX − [P<<PM]) = 0, otherwise, it is cleared.
If the subtraction generates a borrow, C is cleared; otherwise C is set.
The value in the PM bits sets the shift mode for the output operation from the
product register. If the product shift value is positive (logical left shift
operation), then the low bits are zero filled. If the product shift value is
negative (arithmetic right shift operation), the upper bits are sign extended.
This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
ACC,@VarA
−4
P,@VarB
ACC,P << PM
OPCODE OBJMODE
; ACC = VarA
; Set the product shift mode to ">> 4"
; P = VarB
; Compare (VarA − VarB >> 4)
CMPL ACC,P << PM
Compare 32-bit Value
RPT CYC
X − 1
6-81