Texas Instruments TMS320C28x Reference Manual page 182

Dsp cpu and instruction set
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ADD ACC,loc16 << #0..16
SYNTAX OPTIONS
ADD ACC,loc16<<#0
ADD ACC,loc16 << #1..15
ADD ACC,loc16 << #16
ADD ACC,loc16<<0...15
Operands
ACC
loc16
#0..16
Description
Flags and
g
Z
Modes
N
C
V
OVC
SXM
OVM
Repeat
1000 0001 LLLL LLLL
0101 0110 0000 0100
0000 SHFT LLLL LLLL
0000 0101 LLLL LLLL
1010 SHFT LLLL LLLL
Accumulator register
Addressing mode (see Chapter 5)
Shift value (default is "<< #0" if no value specified)
Add the left shifted 16-bit location pointed to by the "loc16" addressing mode
to the ACC register. The shifted value is sign extended if sign extension
mode is turned on (SXM = 1) else the shifted value is zero extended
(SXM = 0). The lower bits of the shifted value are zero filled:
if(SXM = 1)
ACC = ACC + S:[loc16] << shift value;
else
ACC = ACC + 0:[loc16] << shift value;
After the addition, the Z flag is set if ACC is zero, else Z is cleared.
After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared.
If the addition generates a carry, C is set; otherwise C is cleared.
Exception: If a shift of 16 is used, the ADD instruction can set C but not clear C.
If an overflow occurs, V is set; otherwise V is not affected.
If (OVM = 0, disabled) then if the operation generates a positive overflow, then
the counter is incremented and if the operation generates a negative
overflow, then the counter is decremented. If (OVM = 1, enabled) then the
counter is not affected by the operation.
If sign extension mode bit is set; then the 16-bit operand, addressed by the
"loc16" field, will be sign extended before the addition. Else, the value will be
zero extended.
If overflow mode bit is set; then the ACC value will saturate maximum positive
(0x7FFFFFFF) or maximum negative (0x80000000) if the operation
overflowed.
If the operation is repeatable, then the instruction will be executed N+1
times. The state of the Z, N, C flags will reflect the final result. The V flag will
be set if an intermediate overflow occurs. The OVC flag will count
intermediate overflows, if overflow mode is disabled. If the operation is not
repeatable, the instruction will execute only once.
Add Value to Accumulator
OPCODE
// sign extension mode enabled
// sign extension mode disabled
ADD ACC,loc16 << #0..16
OBJMODE
RPT
CYC
1
Y
N+1
1
Y
N+1
X
Y
N+1
0
N+1
6-25

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