Texas Instruments TMS320C28x Reference Manual page 60

Status Register (ST0)
TC
Test/control flag. This bit shows the result of a test performed by either the TBIT (test bit)
instruction or the NORM (normalize) instruction.
Bit 2
The TBIT instruction tests a specified bit. When TBIT is executed, the TC bit is set if the
tested bit is 1 or cleared if the tested bit is 0.
When a NORM instruction is executed, TC is modified as follows: If ACC holds 0, TC is set.
If ACC does not hold 0, the CPU calculates the exclusive-OR of ACC bits 31 and 30, and
then loads TC with the result.
This bit can be individually set and cleared by the SETC TC instruction and CLRC TC
instruction, respectively. At reset, TC is cleared.
2-30
Table 2−8. Bits Affected by the C Bit (Continued)
Instruction
SUBBL ACC,loc32
SUBCU ACC,loc16
SUBCUL ACC,loc32
SUBL ACC,loc32
SUBL loc32,ACC
SUBR loc16,AX
SUBRL loc32,ACC
SUBU ACC,loc16
SUBUL ACC,loc32
SUBUL P,loc32
XB pma,COND
XCALL pma,COND
XMAC P,loc16,*(pma)
XMACD P,loc16,*(pma)
XRETC COND
Table 2−9 lists the instructions that affect the TC bit. See the instruction set in
Chapter 6 for a complete description of each instruction.
Affect of or Affect on C
ACC = ACC − ([loc32] + ~C)
C = 0 on borrow else C = 1
for(ACC − [loc16]<<15)
C = 0 on borrow else C = 1
for(ACC<<1 + P(31) − [loc32])
C = 0 on borrow else C = 1
C = 0 on borrow else C = 1
C = 0 on borrow else C = 1
C = 0 on borrow else C = 1
C = 0 on borrow else C = 1
C = 0 on borrow else C = 1
C = 0 on borrow else C = 1
C = 0 on borrow else C = 1
C bit used as test condition
C bit used as test condition
C = 1 on carry else C = 0
C = 1 on carry else C = 0
C bit used as test condition