C2Xlp And C28X Differences In Status Registers - Texas Instruments TMS320C28x Reference Manual

Table D−6. C2xLP and C28x Differences in Interrupts (Continued)
Migration topic
8 Interrupt enable and return
from function call
9 Interrupts Vector
10 Context save
Table D−7. C2xLP and C28x Differences in Status Registers
Migration topic
1 Saving ST0/ST1 registers
2 ST0/ST1 bit differences
Reference Tables for C2xLP Code Migration Topics
C2xLP
CLRC INTM
next_instn
Uses Branch statements at the
vector address.
Ex: B Start ;assembly
;code
opcode in memory
0x7980 ;branch
;instruction
0x0040 ;branch
;address
No automatic context save
See section D.3 for a full context
save/restore example
C2xLP
Save:
SST #0,mem ;store ST0
SST #1,mem ;store ST1
Restore:
LST #0,mem ;load ST0
LST #1,mem ;load ST1
ST0/ST1 bits have CPU registers
and status bits
C28x
next_instn
CLRC INTM
32−bit absolute addresses.
; code in vector location
0x0040 (low address)
;
0x003F (high address)
Automatic context save of CPU regis-
ters T, ST0, AH, AL, PH, PL, AR1,
AR0, DP, ST1, DBGSTAT, IER, PC
See Table D−5 for a full context save/
restore example
C28x
Save:
PUSH ST ;store ST0 to stack
PUSH ST ;store ST1 to stack
Restore:
POP ST1 ;load ST1
;from stack
POP ST0 ;load ST0
;from stack
ST0/ST1 bits are rearranged
compared to C2xLP registers.
C2xLP Migration Guidelines D-11