Texas Instruments TMS320C28x Reference Manual page 492

SUB ACC,loc16 <<T
SYNTAX OPTIONS
SUB ACC,loc16 <<T
Operands ACC
loc16
T
Description
Flags and Z
Modes
N
C
V
OVC
SXM
OVM
Repeat
0101 0110 0010 0111
0000 0000 LLLL LLLL
Accumulator register
Addressing mode (see Chapter 5)
Upper 16−bits of the multiplicand register, XT(31:16)
Subtract from the ACC register the left−shifted contents of the 16-bit location
pointed to by the "loc16" addressing mode. The shift value is specified by the
four least significant bits of the T register, T(3:0) = shift value = 0..15. Higher
order bits are ignored. The shifted value is sign extended if sign extension
mode is turned on (SXM=1) else the shifted value is zero extended (SXM=0).
The lower bits of the shifted value are zero filled:
if(SXM = 1)
ACC = ACC − S:[loc16] << T(3:0);
else
ACC = ACC − 0:[loc16] << T(3:0);
After the subtraction, the Z flag is set if the ACC value is zero, else Z is
cleared.
After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is
cleared.
If the subtraction generates a borrow, C is cleared; otherwise C is set.
If an overflow occurs, V is set; otherwise V is not affected.
If(OVM = 0, disabled) then if the operation generates a positive overflow,
then the counter is incremented and if the operation generates a negative
overflow, then the counter is decremented. If(OVM = 1, enabled) then the
counter is not affected by the operation.
If sign extension mode bit is set; then the 16-bit operand, addressed by the
"loc16" field, will be sign extended before the addition. Else, the value will be
zero extended.
If overflow mode bit is set; then the ACC value will saturate maximum
positive (0x7FFF FFFF) or maximum negative (0x8000 0000) if the
operation overflowed.
If this operation is repeated, then the instruction will be executed N+1 times.
The state of the Z, N, C flags will reflect the final result. The V flag will be set if
an intermediate overflow occurs. The OVC flag will count intermediate
overflows, if overflow mode is disabled.
Subtract Shifted Value From Accumulator
OPCODE
// sign extension mode enabled
// sign extension mode disabled
SUB ACC,loc16 <<T
OBJMODE RPT CYC
1 Y N+1
6-335