Texas Instruments TMS320C28x Reference Manual page 5

Dsp cpu and instruction set
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value from 0 to 5; where the 6bit appears, you type a 6-bit constant. The
rest of the instruction, including the square brackets, must be entered as
shown.
When braces or brackets enclose an operand, as in {operand}, the oper-
-
and is optional. If you use an optional operand, you specify the information
within the braces; you do not enter the braces themselves. In the following
syntax, the operand << shift is optional:
MOV ACC, *−SP[6bit] {<< shift }
MOV ACC, *−SP{6bit} {<< shift }
For example, you could use either of the following instructions:
MOV ACC, *−SP[5]
MOV ACC, *−SP[5]<< 4
In most cases, hexadecimal numbers are shown with a subscript of 16. For
-
example, the hexadecimal number 40 would be shown as 40
tion to this rule is a hexadecimal number in a code example; these hexade-
cimal numbers have the suffix h. For example, the number 40 in the follow-
ing code is a hexadecimal 40.
MOVB AR0,#40h
Similarly, binary numbers usually are shown with a subscript of 2. For ex-
ample, the binary number 4 would be shown as 0100
example code have the suffix b. For example, the following code uses a
binary 4.
MOVB AR0,#0100b
Bus signals and bits are sometimes represented with the following nota-
-
tions:
Notation
Description
Bus(n:m)
Signals n through m of bus
Register(n:m)
Bits n through m of register
Register(n)
Bit n of register
Notational Conventions
. An excep-
16
. Binary numbers in
2
Example
PRDB(31:0) represents the 32
signals of the program-read data
bus (PRDB).
T(3:0) represents the 4 least sig-
nificant bits of the T register.
IER(4) represents bit 4 of the in-
terrupt enable register (IER).
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