Texas Instruments TMS320C28x Reference Manual page 67

DBGM Debug enable mask bit. When DBGM is set, the emulator cannot accesss memory or
registers in real time. The debugger cannot update its windows.
Bit 1
In the real-time emulation mode, if DBGM = 1, the CPU ignores halt requests or hard-
ware breakpoints until DBGM is cleared. DBGM does not prevent the CPU from halting
at a software breakpoint. One effect of this may be seen in real-time emulation mode.
If you single-step an instruction in real time emulation mode and that instruction sets
DBGM, the CPU continues to execute instructions until DBGM is cleared.
When you give the TI debugger the REALTIME command (to enter real-time mode),
DBGM is forced to 0. Having DBGM = 0 ensures that debug and test direct memory
accesses (DT-DMAs) are allowed; memory and register values can be passed to the
host processor for updating debugger windows.
Before the CPU executes an interrupt service routine (ISR), it sets DBGM. When
DBGM = 1, halt requests from the host processor and hardware breakpoints are ig-
nored. If you want to single-step through or set breakpoints in a non-time-critical ISR,
you must add a CLRC DBGM instruction at the beginning of the ISR.
DBGM is primarily used in emulation to block debug events in time-critical portions of
program code. DBGM enables or disables debug events as follows:
0
1
When the CPU services an interrupt, the current value of DBGM is saved on the stack
(when ST1 is saved on the stack), and then DBGM is set. Upon return from the inter-
rupt, DBGM is restored from the stack.
This bit can be individually set and cleared by the SETC DBGM instruction and
CLRC DBGM instruction, respectively. DBGM is also set automatically during interrupt
operations. At reset, DBGM is set. Executing the ABORTI (abort interrupt) instruction
also sets DBGM.
INTM Interrupt global mask bit. This bit globally enables or disables all maskable CPU inter-
rupts (those that can be blocked by software):
Bit 0
0
1
INTM has no effect on the nonmaskable interrupts, including a hardware reset or the
hardware interrupt NMI. In addition, when the CPU is halted in real-time emulation
mode, an interrupt enabled by the IER and the DBGIER will be serviced even if INTM is
set to disable maskable interrupts.
Debug events are enabled.
Debug events are disabled.
Maskable interrupts are globally enabled. To be acknowledged by the CPU, a
maskable interrupt must also be locally enabled by the interrupt enable register
(IER).
Maskable interrupts are globally disabled. Even if a maskable interrupt is local-
ly enabled by the IER, it is not acknowledged by the CPU.
Status Register ST1
Central Processing Unit 2-37