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Table E−2. C2xLP Instructions and C28x Equivalent Instructions (Continued)
C2xLP
Instruc-
Mnemonic
tion
RET
RETC
COND
RETC
COND1,COND2,..,CONDn
ROL
ROR
RPT
loc16
RPT
#8bit
SACH
loc16[,0]
SACH
loc16,1
SACH
loc16,2..7
SACL
loc16[,0]
SACL
loc16,1
SACL
loc16,2..7
SAR
ARn,loc16
SBRK
#8bit
SETC
INTM
SETC
XF/OVM/SXM/TC/C
SETC
CNF
SFL
SFR
SPAC
SPH
loc16
SPL
loc16
†
True/False
Cycles
Size
Instruc-
tion
4
16
XRETC
†
4/2
XRETC
4/2
16
SB
SB
.
XRETC
$10:
n+l
16
ROL
n+l
16
ROR
1
16
RPT
1
16
RPT
n+l
16
MOV
n+l
16
MOVH
n+l
16
MOVH
n+l
16
MOV
n+l
16
MOV
n+l
16
MOV
n+l
16
MOV
1
16
SBRK
n+l
16
SETC
n+l
16
SETC
n+l
16
n+l
16
LSL
n+l
16
SFR
n+l
16
SUB
n+l
16
MOVH
n+l
16
MOV
C2xLP Instruction Set Compatibility
Condition Tests on Flags
C28x
Mnemonic
UNC
COND
$10,opposite of COND1
$10,opposite of COND2
.
CONDn
ACC
ACC
loc16
#8bit
loc16,AH
loc16,ACC << 1
loc16,ACC << 2..7
loc16,AL
loc16,ACC << 1
loc16,ACC << 2..7
loc16,ARn
#8bit
INTM
XF/OVM/SXM/TC/C
Not applicable
ACC,1
ACC,1
ACC,P<<PM
loc16,P
loc16,P
Cycles
Size
7
16
7/4
16
7+
48+
n+1
16
n+1
16
1
16
1
16
n+1
16
n+1
16
n+1
32
n+1
16
n+1
16
n+1
32
1
16
1
16
2
16
2,1
16
n+1
16
n+1
16
n+1
16
n+1
16
n+1
16
E-7
- Quick Links:
- 1.1 Introduction to the Cpu
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