Texas Instruments TMS320C28x Reference Manual page 271

INTR
INTR
SYNTAX OPTIONS
INTR INTx
INTR DLOGINT
INTR RTOSINT
INTR NMI
INTR EMUINT
Operands INTx
DLO-
GINT
RTOSINT Maskable CPU real-time operating system interrupt
NMI
EMUINT
Description
INTx
where x =
0
1
2
3
4
5
6
7
8
6-114
0000 0000 0001 CCCC
0000 0000 0001 CCCC
0000 0000 0001 CCCC
0111 0110 0001 0110
0111 0110 0001 1100
Maskable CPU interrupt vector name, x = 1 to 14
Maskable CPU datalogging interrupt
Nonmaskable interrupt
Maskable emulation interrupt
Emulate an interrupt. The INTR instruction transfers program control to
the interrupt service routine that corresponds to the vector specified by the
instruction. The INTR instruction is not affected by the INTM bit in status
register ST1. It is also not affected by enable bits in the interrupt enable
register (IER) or the debug interrupt enable register (DBGIER). Once the
INTR instruction reaches the decode 2 phase of the pipeline, hardware
interrupts cannot be serviced until the INTR instruction is finished
executing (until the interrupt service routine begins).
Interrupt
Vector
RESET
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
Emulate Hardware Interrupt
OPCODE
INTx
where x =
9
10
11
12
13
14
OBJMODE RPT CYC
X − 8
X − 8
X − 8
X − 8
X − 8
Interrupt
Vector
INT9
INT10
INT11
INT12
INT13
INT14