Program Space Indirect Addressing Modes
5.9 Program Space Indirect Addressing Modes
Syntax
*AL
Instructions that use this addressing mode:
XPREAD
loc16,*AL
XPWRITE *AL,loc16
Syntax
*XAR7
Instructions that use this addressing mode:
MAC
P,loc16,*XAR7
DMAC
ACC:P,loc32,*XAR7 ; ACC = ([loc32].MSW * ProgSpace[*XAR7].MSW) >> PM,
QMACL
P,loc32,*XAR7
IMACL
P,loc32,*XAR7
PREAD
loc16,*XAR7
PWRITE *XAR7,loc16
Syntax
*XAR7++
Instructions that use this addressing mode:
MAC
P,loc16,*XAR7++
DMAC
ACC:P,loc32,*XAR7++ ; ACC=([loc32].MSW * ProgSpace[*XAR7++].MSW)>>PM,
QMACL P,loc32,*XAR7++
IMACL P,loc32,*XAR7++
5-30
Description
22BitProgAddr(21:16) = 0x3F
22BitProgAddr(15:0) = AL
Note:
If instruction is repeated, the address in AL is copied to a shadow register and the
value post−incremented on each iteration. The AL register is not modified. This ad-
dressing mode can only access the upper 64K of program space.
; [loc16] = ProgSpace[0x3F:AL]
; ProgSpace[0x3F:AL] = [loc16]
Description
22BitProgAddr(21:0) = XAR7
Note:
If instruction is repeated, only in the XPREAD and XPWRITE instructions, is the ad-
dress contained in XAR7 copied to a shadow register and the value post−increm-
ented on each iteration. The XAR7 register is not modified. For all other instructions,
the address is not incremented even when repeated.
; ACC = ACC + P << PM,
; P = [loc16] * ProgSpace[*XAR7]
; P = ([loc32].LSW * ProgSpace[*XAR7].MSW) >> PM
; ACC = ACC + P >> PM,
; P = ([loc32] * ProgSpace[*XAR7]) >> 32
; ACC = ACC + P,
; P = ([loc32] * ProgSpace[*XAR7]) << PM
; [loc16] = ProgSpace[*XAR7]
; ProgSpace[*XAR7] = [loc16]
Description
22BitProgAddr(21:0) = XAR7,
if(16−bit operation) XAR7 = XAR7 + 1,
if(32−bit operation) XAR7 = XAR7 + 2
Note:
If instruction is repeated, the address is post−incremented as normal.
; ACC = ACC + P << PM,
; P = [loc16] * ProgSpace[*XAR7++]
; P=([loc32].LSW * ProgSpace[*XAR7++].MSW)>>PM
; ACC = ACC + P >> PM,
; P = ([loc32] * ProgSpace[*XAR7++]) >> 32
; ACC = ACC + P,
; P = ([loc32] * ProgSpace[*XAR7++]) << PM
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