Texas Instruments TMS320C28x Reference Manual page 685

Index
data-/program-write data bus (DWDB) 1-9
data-read address bus (DRAB) 1-9
data-read data bus (DRDB) 1-9
data-write address bus (DWAB) 1-9
DBGIER A-2
DBGM F-4
debug enable mask bit C-9
DBGSTAT register 7-15
debug
enable mask bit (DBGM) 2-37
event 7-6
execution control modes 7-7
halt state 7-6
interface 7-3
sharing resources 7-30
terminology 7-6
debug enable mask bit (DBGM) 2-37
role in accesses during emulation 7-16
set during interrupt handling 3-15, 3-20
debug interrupt enable register A-2
debug interrupt enable register (DBGIER) 3-6, 3-8,
3-10, 7-9
quick reference figure A-9
Debug interrupt−enable register C-4
debug status register (DBGSTAT) 7-15
debug−and−test direct memory access 1-5
debug-and-test direct memory access (DT-DMA)
mechanism 7-16
debug-halt state 7-7, 7-9
DEC loc16 6-84
decoupled pipeline segments 4-4
decrement by 1 6-84
development interface 7-2
diagnostic features for emulation 7-31
diagrams
CPU 2-3
memory map 1-7
multiplication 2-42, 2-43
pipeline activity 4-8
pipeline conflict 4-13, 4-14
relationship between pipeline and address count-
ers 4-6
shift operations 2-45
T320C28x DSP core 1-4
DINT 6-85
Direct Addressing Mode 5-2, 5-8
Index-4
direct addressing mode C-5
Direct Addressing Mode Mapping, figure C-6
direct addressing mode on the C2xLP C-5
direct memory access mechanism
for emulation 7-16
disable write access to protected registers 6-91
discontinuity delay 4-11
DMA control register 7-25
DMA ID register 7-25
DMA registers (data logging) 7-25
DMAC ACC:P,loc32,*XAR7 6-86
DMOV loc16 6-89
DP 2-10
DT−DMA 1-5
DT-DMA mechanism 7-16
DT-DMA request process, figure 7-17
dual multiply and accumulate 6-86
E
EALLOW 6-90, C-9
EALLOW bit 2-35
EALLOW instruction, use in
data logging 7-23, 7-26
EDIS 6-91
EDIS instruction, use in data logging 7-24, 7-27
EINT 6-92
EMU0/1, signals 7-4
EMU0/1 signals 7-4
emulation
data logging 7-23
disabled 7-5
enabled 7-5
features 1-5, 7-2
logic 1-4, 1-5, 7-15
Emulation access enable bit C-9
emulation access enable bit (EALLOW) 2-35
emulation signals 1-6
enable maskable interrupts 6-92
enable write access to protected space 6-90
end address register (data logging) 7-26
ESTOP0 6-93
ESTOP1 6-94
event counter 7-20
events
break 7-6