Texas Instruments TMS320C28x Reference Manual page 683

Index
AND ACC, loc16 6-43, 6-44
AND AX, loc16, #16bit 6-45
AND IER,#16bit 6-46
AND IFR,#16bit 6-47
AND loc16, AX 6-48
AND AX, loc16 6-49
AND IER and OR IER instructions, note
about RTOSINT 3-9
AND loc16,#16bitSigned 6-50
ANDB AX, #8bit 6-51
architectural overview 1-1
architecture differences between the
C27x and the C28x F-1
architecture differences between the
C2xLP and the C28x C-1
arithmetic logic unit (ALU) 1-5
arithmetic shift right 6-53
ARP C-9
ARx registers D-14
ASP 6-52
ASR AX,#1016 6-53
ASR AX,T 6-54
ASR64 ACC:P,#1..16 6-55
ASR64 ACC:P,T 6-56
ASRL ACC,T 6-57
atomic arithmetic logic unit (ALU) 2-2
Auxiliary registers C-4
auxiliary registers
AR0−AR5, XAR6, XAR7 2-12
pointer 2-34
B
B 16bitOffset,COND 6-58
B0 Memory Map C-14
background code 7-6
BANZ E-4
BANZ 16bitOffset,ARn−− 6-59
BAR 16bitOffset,ARn,ARm,EQ 6-60
barrel shifter 1-5
benchmark counter 7-20
BF 16bitOffset,COND 6-61
bits
auxiliary register pointer (ARP) 2-34
carry (C) 2-25
Index-2
debug enable mask (DBGM) 2-37
debug interrupt enable register (DBGIER) 3-10
emulation access enable (EALLOW) 2-35
IDLE status (IDLESTAT) 2-35
interrupt enable register (IER) 3-9
interrupt flag register (IFR) 3-7
interrupt global mask (INTM) 2-37
loop instruction status (LOOP) 2-35
negative flag (N) 2-24
overflow counter (OVC) 2-16
overflow flag (V) 2-21
overflow mode (OVM) 2-32
PAGE0 addressing mode configuration 2-36
product shift mode (PM) 2-19
sign-extension mode 2-32
stack pointer alignment (SPA) 2-36
test/control flag (TC) 2-30
vector map (VMAP) 2-36
zero flag (Z) 2-25
block diagram of the CPU, figure 2-3
branch 6-58
instructions introduced 2-39
break event 7-6
break events 7-7
breakpoints 7-19
caution about time-critical ISRs 7-11
Building a C27x Object File From C27x Source,
figure F-8
buses
data-/program-write data 1-9
data-read address 1-9
data-read data 1-9
data-write address 1-9
program address 1-9
program-read data 1-9
special operations 1-10
summary table 1-10
C
C bit 2-25
C27MAP 6-62
C27OBJ 6-63
C27x Compatible Mapping of ABlocks M0 and M1,
figure F-7
C27x object mode F-8
C28ADDR 6-64
C28MAP 6-65
C28OBJ 6-66