Emulation Logic - Texas Instruments TMS320C28x Reference Manual

1.2.2

Emulation Logic

registers, math registers, and data pointers. The system-control registers
are accessed by special instructions. The other registers are accessed by
special instructions or by a special addressing mode (register addressing
mode).
Arithmetic logic unit (ALU). The 32-bit ALU performs 2s-complement arith-
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metic and Boolean logic operations.
Address register arithmetic unit (ARAU). The ARAU generates data-
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memory addresses and increments or decrements pointers in parallel with
ALU operations.
Barrel shifter. This shifter performs all left and right shifts of data. It can shift
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data to the left by up to 16 bits and to the right by up to 16 bits.
Multiplier. The multiplier performs 32-bit × 32-bit 2s-complement multi-
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plication with a 64-bit result. The multiplication can be performed with two
signed numbers, two unsigned numbers, or one signed number and one
unsigned number.
The emulation logic includes the following features. For more details about
these features, see Chapter 7, Emulation Features.
Debug-and-test direct memory access (DT-DMA). A debug host can gain
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direct access to the content of registers and memory by taking control of
the memory interface during unused cycles of the instruction pipeline.
Data logging. The emulation logic enables application-initiated transfers
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of memory contents between the C28x and a debug host.
A counter for performance benchmarking
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Multiple debug events. Any of the following debug events can cause a
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break in program execution:
A breakpoint initiated by the ESTOP0 or ESTOP1 instruction
J
An access to a specified program-space or data-space location
J
A request from the debug host or other hardware
J
When a debug event causes the C28x to enter the debug-halt state, the
event is called a break event.
Real-time mode of operation. When the C28x is in this mode and a break
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event occurs, the main body of program code comes to a halt, but time-crit-
ical interrupts can still be serviced.
Components of the CPU
Architectural Overview 1-5